The disclosed embodiments relate to a semiconductor memory device, semiconductor package and system, and more particularly, to a semiconductor memory device, semiconductor package, and system having a plurality of stack-structured semiconductor chips.
Semiconductor memory devices that have come into widespread use as storage devices for electronic systems are increasing in capacity and operating speeds. Various attempts have been made to mount a higher capacity of memory on a smaller area and to run the memory at higher speeds.
For example, in order to increase the capacity of a semiconductor memory device, a plurality of semiconductor chips each having a memory cell are stacked within one semiconductor memory device. In general, when a plurality of semiconductor chips are included in a semiconductor memory device, one of the semiconductor chips acts as a master chip and the other semiconductor chips act as slave chips. The master chip exchanges data with an external memory controller or receives various control signals and voltage signals from the external memory controller. To this end, the master chip includes a peripheral region for controlling memory operations by using various control signals and voltage signals received from external sources, providing read data to external devices, or receiving write data from external sources. Also, each of the slave chips includes a pad region that interfaces with the master chip in order to receive various control signals or write data from the master chip or in order to provide read data to the master chip.
The semiconductor memory device is fabricated in the form of a package, and the semiconductor package is mounted on the memory module or system board and may communicate with the external memory controller via conductive devices, e.g., solder balls or leads, which are attached to an external surface of the memory package. Also, in general, a supply voltage and a ground voltage that are used for memory operations are applied to each of the semiconductor chips from the external memory controller via the conductive devices.
When the supply or ground voltage is applied to the memory package, then the supply or ground voltage is transferred to each of the semiconductor chips via a conductive line formed in the semiconductor memory device. In this case, resistance occurs in a path in which such a voltage signal is applied, caused by the physical properties of the conductive line. If higher resistance occurs in this path, the intensity of noise generated in the supply or ground voltage transferred to each of the semiconductor chips also increases. If a high intensity of noise occurs in the supply or ground voltage applied inside a region having a memory cell, memory operating characteristics are degraded. In particular, even if a low intensity of noise is generated in the supply or ground voltage applied to a semiconductor memory device in which a plurality of semiconductor chips are mounted on a small area, then not only the memory characteristics of the semiconductor memory device may be degraded greatly but also the performance of the plurality of semiconductor chips may be degraded.